OpenRISC development board from ORSoC

An Open Parallel Hardware Project

We would like to encourage everyone to check out and (if you like) help this project via Kickstarter.

Parallella project Kickstarter,

Making parallel computing easy to use has been described as "a problem as hard as any that computer science has faced". We need to make sure that every programmer has access to cheap and open parallel hardware and development tools.

This project will design a truly open, high-performance computing platform that will close the knowledge gap in parallel programming. The goal of the Parallella project is to democratize access to parallel computing.

Only a few days act fast!!!


Update from OC-Team

This topic gives you an update of what has been "cooking" at the OpenCores community during the last month.


New IP-cores at OpenCores

View a list of all interesting new projects that have reached a first stage of development.
This time: 5 new projects


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Newsletter October 2012

Parallella: A $100 Computer Based on the Zynq FPGA and Epiphany Multicore

Heterogeneous computing for everyone - Parallella
Lexington, MA, October 24, 2012 – Adapteva today announced that the official host processor used on the Parallella computing platform, launched through Kickstarter, is the Zynq Extensible Processing Platform (EPP) from Xilinx®. The Parallella platform combines a Zynq-7000 EPP platform that includes an industry-standard ARM® dual-core Cortex™-A9 processing system with Adapteva’s Epiphany multicore processors to provide a low cost computing platform with unprecedented performance and flexibility.

The Parallella board includes a Zynq7010 dual-core Cortex™-A9 processing system, 1GB SDRAM, an Epiphany multicore accelerator, Gigabit Ethernet, two USB 2.0 ports, and an HDMI video port, and extensive general purpose IO directly connected to the Zynq parallel logic fabric. The performance, flexibility, high off-board bandwidth, and price point of the Parallella board could enable amazing new applications in embedded vision, software defined radio, medical imaging, and consumer electronics.

Two board flavors will be offered, with the differentiating feature being the type of Epiphany accelerator chip included: an entry version incorporating the 16-core Epiphany-III processor with up to 13 GFLOPS of performance at 800MHz, and a high performance version using the 64-core Epiphany-IV processor with up to 90 GFLOPS of peak performance at 700Mhz. The Parallella offers developers server-level performance within a credit card sized board footprint.

Adapteva’s 64-core Epiphany-IV 28nm processor scored an impressive 78,748.80 on the ANSI-C CoreMark® benchmark from EEMBC®. At a mere 2 Watt power consumption, this is a fraction of the power consumed by traditional high performance multicore microprocessors.

The Parallella boards will ship with a Linux Ubuntu distribution and an open source SDK for developing applications for the Epiphany architecture using C, C++ and/or OpenCL. Software development tools, drivers and libraries will be provided under a true open source license. Board design files and board support packages for the Parallella computer will be delivered to the public in open source format and available for everyone to use free of charge and without restrictions.

The Parallella Kickstarter campaign runs through October 27th. For more information go to or to the Kickstarter campaign page.

About Adapteva
Adapteva, Inc. is a privately-held semiconductor technology company based in Lexington, Massachusetts. Adapteva has developed the world’s most energy efficient multicore microprocessor architecture, immediately boosting by an order of magnitude the number of cores that can be integrated on a single chip. Adapteva’s breakthrough architecture will have an immediate impact on a wide range of end-user products, from compact mobile devices to next generation supercomputers. For more information on the company visit Also find us on twitter @adapteva or @parallellaboard and

ORSoC-team, ORSoC

Update from OC-Team

This topic gives you an update of what has been "cooking" at the OpenCores community during the last month.

This month activities:

Website information:

  • Some minor issues

Server information:

  • Added additional harddrives.

Our message to the community:

  • Support the open-source hardware Kickstarter project - The Parallella project
  • Help us improve the community, please provide feedback

Marcus Erlandsson, ORSoC

New IP-cores

Here you will see interesting new projects that have reached the first stage of development.


AES (Advanced Encryption Standard) is a specification published by the American National Institute of Standards and Technology in 2001, as FIPS 197.[1]

AES describes a symmetric-key algorithm, in which the same key is used for both encrypting and decrypting the data. The block size is restricted to 128 bits. The key size can be 128, 192, or 256 bits. [1]

AES operates on a 4×4 matrix of bytes, called the state. Some rounds of transformation converts the plaintext into the final cipher-text. The number of rounds is six plus the key size divided by 32. One round reads the state into four 4-byte variables y_0,y_1,y_2,y_3; transforms the variables; xor’s them by a 16-byte round key; and puts the result into z_0,z_1,z_2,z_3.[3]

When targeting a variable-length plaintext, the plaintext must first be partitioned into separate cipher blocks, and then be encrypted under some mode of operation, generally using randomization based on an additional initialization vector.[4]

The cipher feedback (CFB) mode, output feedback (OFB) mode are specified in FIPS 81. The counter (CTR) mode is specified by NIST in SP800-38A.[4] The advantage of these modes is only using encryption algorithm for both encryption and decryption. So the AES hardware price may be reduced by 50% (not need decryption hardware).

This project has implemented AES encryption algorithm.

This project provides three cores, doing AES-128, AES-192 and AES-256 encryption separately.

The cores can be used in cipher feedback (CFB) mode, output feedback (OFB) mode, and counter (CTR) mode.

- Pipeline architecture
- Ultra high speed
- Fully synchronous design
- Fully synthesize-able
- ONLY ONE clock domain in entire core
- NO latch
- All output signals are buffered
- Vendor-independent code

The maximum frequency is 324.6 MHz (on Xilinx FPGA XC6VLX240T, for all of AES-128, AES-192 and AES-256 implementation).
The core can encrypt 128 bytes per clock cycle. The throughput is 37.5 Gbytes/second if it is working with a 300 MHz clock.

Development status: Stable
License: Others
Oct 19, 2012 Update project status
Oct 18, 2012 Upload specification document
Oct 17, 2012 Update description
Oct 17, 2012 Update description
Oct 17, 2012 Update description
Oct 16, 2012 Update synthesis result
Oct 16, 2012 Update synthesis result
Oct 15, 2012 Update synthesis result of AES-256
Oct 14, 2012 Update project info web page
Oct 14, 2012 Update RTL code

Heap sorter for FPGA
This project implements a sorter able to sort a continuous stream of data, consisting of records labeled with "sort keys". Sorter sorts one record every two clock cycles.
Sorter is based on the heap sort algorithm. Efficient implementation is assured thanks to the use of internal dual port RAM in FPGA.
The required size of heap is equal to the expected maximum distance between unsorted records in the data stream.

Development status: Beta
License: BSD
Oct 15, 2012 Detailed description modified
Oct 15, 2012 added initial description

MIPS32 Release 1
A 32-bit MIPS processor conforming to the MIPS32 Release 1 ISA. This processor implementation was designed and built by Grant Ayers as part of the eXtensible Utah Multicore (XUM) project at the University of Utah, 2011-2012.

- Pipelined (5-stage) with full forwarding and hazard detection.
- Harvard architecture (separate instruction and data ports which can be combined if desired).
- Memory interface is separate from the processor for flexibility with connecting various RAMs.
- Complete Coprocessor 0 for ISA-compliant interrupts, exceptions, and user/kernel modes.
- No MMU and no FPU, but the toolchain allows software-based floating point.
- Hardware divide is supported in the design but not implemented for logic space reasons.
- Hardware is Big-Endian by default and supports reverse-endian mode for User mode.
- All other required instructions are implemented, including atomic load linked / store conditional (ll, sc) and unaligned loads and stores (lwl, swr, etc).
- Parameterized addresses for exception/interrupt vectors and boundary address between user/kernel regions.
- Extensive documentation in-source and elsewhere.
- Vendor-independent code.
- A clean, modular design written from scratch.

The project includes a standalone MIPS32 processor as well as a full System-on-Chip design targeted for the XUPV5-LX110T board. With minor changes (clock module, BRAM module, and pin constraints) the SoC can run on many hardware platforms.

The standalone processor utilizes approximately 1,800 slice registers (2%) and 4,000 LUTs (5%) on a Virtex 5 LX110T. The SoC utilizes approximately 2,700 slice registers (3%) and 5,100 LUTs (7%) on a Virtex 5 LX110T.

Other Inclusions
The following MMIO hardware drivers are included as part of the SoC design:
- Basic single-master I2C driver.
- 16x2 LCD driver for Sitronix ST7066U, Samsung S6A0069X / KS0066U, Hitachi HD44780, SMOS SED1278, or other compatible hardware.
- LED driver.
- Piezo transducer driver.
- Switch input filter.
- 115200 baud 8-N-1 serial port using only Tx and Rx with configurable baud rate.
- 592 KB BRAM and clock generation for XUPV5 board.

The following software is included:
- XUM bootloader which loads programs from a PC to the FPGA. This is written in C# for Windows, however the boot protocol is simple and can be implemented in any operating system or not used at all.
Software Toolchain
The software toolchain is based on Binutils, GCC, and Newlib. It can be built for almost any platform, including unix-like environments and Windows (Cygwin). Instructions are included with the project.
The current toolchain uses Binutils 2.21, GCC 4.7.1 (mpfr 3.0.1, mpc 0.9, gmp 5.0.5), and Newlib 1.20.0.
The toolchain currently supports Big- and Little-Endian code as well as software floating point. Newlib C library stubs are left unchanged.

Development status: Stable
License: LGPL
Oct 14, 2012 Added information about included hardware drivers and software.
Oct 14, 2012 Project is written in Verilog, not VHDL.

Flexible Design of a Modular Simultaneous Exponentiation Core

This core is a flexible hardware design for modular simultaneous exponentiations as commonly used in anonymous credential and authentication cryptosystems like DSA, idemix, etc..
The hardware is designed for simultaneous exponentiations but also supports single base exponentiations and single Montgomery multiplications.
The kernel of this design is a pipelined Montgomery multiplier . The length of the operands and the number of pipeline stages can be chosen before synthesis. To further increase the flexibility, 3 different operand lengths are supported in runtime.
The goal of this project is to develop a general core that works on different systems and supports various bus interfaces. (AXI, PLB and wishbone)

currently the design is working for the PLB bus, and is being tranferred to the opencores design rules.

Development status: Alpha
License: LGPL
Oct 16, 2012 Updated project status
Oct 16, 2012 Added general description

2nd order Sigma-Delta DAC
Public domain code of the 2nd order Sigma-Delta DAC. Allows to produce reasonable quality audio signal from single digital ouput pin in the FPGA. The resource consumption is very low (24-bit version of the DAC consumed 5% of slices in xc3s200).

Development status: Mature
License: Others
Oct 17, 2012 small correction in detailed description
Oct 16, 2012 added initial description

Johan Rilegård, ORSoC

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