ACEX 1K50 board :: Overview

Project maintainers


Name: acxbrd
Created: Sep 11, 2004
Updated: Dec 20, 2009
SVN Updated: Mar 10, 2009
SVN: Browse
Latest version: download
Statistics: View

Other project properties

Category: Prototype board
Development status: Stable
Additional info: FPGA proven
WishBone compliant: No
WishBone version: n/a
License: GPL


This is a small board with the low-cost ACEX FPGA with some SRAM and Flash. It is designed as a module for soft-core CPU development. I've used this board as basis for JOP - the Java processor. JOP still fits into the ACEX 1K50.

See some pictures of the board at:

The schematic and the PCB layout is provided under GPL.


- Altera ACEX 1K50TC144-3 FPGA
- Voltage regulators (3V3, 2V5)
- Crystal clock (20 MHz)
- 512KB Flash (for FPGA configuration and program)
- 128KB Ram
- Byteblaster port
- Watchdog with LED
- EPM7032 PLD to load FPGA from flash (on watchdog reset)
- Serial interface (MAX323A)
- 56 general IO pins


- Board is final
- Used in several projects
- Single page schematic can be used with the free version of Eagle:

FILE: jopcore.pdf

FILE: jopcore.pdf
- abc

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