boundaries :: Overview

Project maintainers


Name: boundaries
Created: Jul 2, 2004
Updated: Dec 20, 2009
SVN Updated: Mar 10, 2009
SVN: Browse
Latest version: download (might take a bit to start...)
Statistics: View
Bugs: reported / solved

★ Star 0 you like it: star it!

Other project properties

Category: Other
Language: Verilog
Development status: Stable
Additional info: Design done
WishBone compliant: No
WishBone version: n/a


This project is a collection of small designs involved with clock boundaries.
The clock_switch designs are based on an eetimes article.
The bc_fifo_basic design is based on ideas from generic_fifo_dc_gray.


- debouncer: debounce a mechanical switch.
- clock_switch2_basic: select 1 of 2 clocks, no glitches.
- clock_switch3_basic: select 1 of 3 clocks, no glitches.
- clock_switch4_basic: select 1 of 4 clocks, no glitches.
- clock_switch8_basic: select 1 of 8 clocks, no glitches.
- oc_fifo_basic: a one-clock fifo
- bc_fifo_basic: a boundary-crossing fifo
- clock_detect: a clock-active detector
- arbiter: a simple parameterized round-robin arbiter
- random_ff: a ff simulation model for async boundaries


- None of these designs have been verified in silicon.

© copyright 1999-2018, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.