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Details

Name: cavlc
Created: Oct 21, 2011
Updated: Nov 20, 2012
SVN Updated: Nov 4, 2011
SVN: Browse
Latest version: download (might take a bit to start...)
Statistics: View
Bugs: 0 reported / 0 solved
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Other project properties

Category:Arithmetic core
Language:Verilog
Development status:Beta
Additional info:Design done
WishBone compliant: No
WishBone version: n/a
License: LGPL

Description

This IP implements the CAVLC parsing process in ITU-T H.264 (05/2003)

Features

- Compatible with ITU-T H.264 (05/2003), but it do not calculate nC and store TotalCoeff,
you need to add a nC_decoder outside this core.

- New structure for run_before decoder, the core doesn't save Runs in flip-flops and
doesn't need the run_combine process, this feature reduces both cycle and resource.

- this core has a simple interface

- 9 cycles per cavlc block on average(including P frames)

- Fully synchronous design, Fully synthesisable

Status

Documentation

Synthesis results

Push-button synthesis results for various targets.

Altera:
- Cyclone EP3C55F256C6 : 1085 LEs @ 114MHz
- Stratix EP2S15F484C3 : 939 LUTs @ 128MHz

Xilinx:
- Virtex XC4V1X200FF1513-10 : 1467 LUTs @ 96MHz