OpenCores

Diogenes: Student RISC System

Project maintainers

Details

Name: diogenes
Created: Feb 1, 2008
Updated: Dec 20, 2009
SVN Updated: Mar 10, 2009
SVN: Browse
Latest version: download (might take a bit to start...)
Statistics: View
Bugs: 0 reported / 0 solved
Star1you like it: star it!

Other project properties

Category:Processor
Language:VHDL
Development status:Beta
Additional info:FPGA proven
WishBone compliant: No
WishBone version: n/a
License:

Description

This Project was developed within a Computer Architecture Course. It demonstrates a simple RISC architecture. Please note that it was developed on a Sparten-3E Starter Kit and memory in VHDL code is embedded via XILINX specific routines.

Features

- Assembler
- Simulator
- Simple I/O (Leds, Buttons, UART, Hitachi LCD)
- VGA Controller

Status

- presented in class as working