FPGA-based Median Filter
Project maintainers
Details
Name: fpga-median
Created: Mar 18, 2014
Updated: Mar 21, 2014
SVN Updated: Mar 21, 2014
SVN: Browse
Latest version: download (might take a bit to start...)
Statistics: View
Bugs: 0 reported / 0 solved
Created: Mar 18, 2014
Updated: Mar 21, 2014
SVN Updated: Mar 21, 2014
SVN: Browse
Latest version: download (might take a bit to start...)
Statistics: View
Bugs: 0 reported / 0 solved
Star4you like it: star it!
Other project properties
Category:Arithmetic core
Language:Verilog
Development status:Stable
Additional info:
WishBone compliant: No
WishBone version: n/a
License: LGPL
Language:Verilog
Development status:Stable
Additional info:
WishBone compliant: No
WishBone version: n/a
License: LGPL
Description
This implementation project proposes a practical implementation of a Median Filter architecture focused in low-cost FPGA devices. The architecture is based on the research presented in the following paper: http://islab.soe.uoguelph.ca/sareibi/TEACHING_dr/ENG6530_RCS_html_dr/outline_W2014/docs/PAPER_REVIEW_dr/2013_dr/GRAD_drFPGAbasedMedianFilter.pdf
Sorry, but we do not have time to develop a proper architecture document. However the paper presents a brief and at the same time complete description for this implementation design.
© copyright 1999-2018 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.