Configurable FPGA Architecture for Hardware-Software Merge Sorting :: Overview

Project maintainers


Name: fpga_architecture_for_merge_sorting
Created: Jul 7, 2016
Updated: Jul 2, 2017
SVN: No files checked in

Other project properties

Category: Arithmetic core
Language: Verilog
Development status: Planning
Additional info: FPGA proven
WishBone compliant: No
WishBone version: n/a
License: LGPL


A hardware-software FPGA accelerated based solution for very large data set merge sorting. The accelerator uses a FIFO based approach for sorting. The main contributions of the proposed implementation are: configurable FIFO buffers in order to address the variable size of the pre-sorted arrays in the merge sorting algorithm, and FIFO buffer size tailored for reduced memory usage of the software component. It has been implemented on Xilinx Zynq platform.

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