FPGA based Connected Component Analysis-Labeling Algorithm :: Overview

Project maintainers


Name: fpga_based_connected_component_analysis-labeling_algorithm
Created: Oct 16, 2015
Updated: Jun 2, 2017
SVN: No files checked in

Other project properties

Category: Arithmetic core
Language: Verilog
Development status: Stable
Additional info: none
WishBone compliant: No
WishBone version: n/a
License: LGPL


A FPGA-based Connected Component Analysis-Labeling Algorithm

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A FPGA-based, parallel, pipelined, real time, Connected Component Analysis-Labeling
Algorithm. Features:
1. Occupy little FPGA resources, only need less than 20 block rams. Do Not Need External
Memories, like DDR. The algorithm only needs to scan the image once, so it only needs to buffer
less than 20 lines of binarized image.
2. It is a real-time pipelined and parallel algorithm, with a fixed delay time less than 20 lines
of pixel's time. And the number of the Connected Components in the image do not affect the
delay time.
3. When finished scanning a Connected Component, the algorithm will output the statistics:
like area, circumference and location of this Connected Component.
4. High reliability . It can give correct statistics of u, n, m, w shaped Connected Component
with only one time scan.
This project has been finished and FPGA proven.

Source Code

Sorry! I do not know how to upload Source code, So please send me a email:
and I will send you the source code

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