FT816Float - Floating point accelerator :: Overview

Project maintainers


Name: ft816float
Created: Dec 9, 2014
Updated: Dec 9, 2016
SVN Updated: Dec 9, 2016
SVN: Browse
Latest version: download
Statistics: View

Other project properties

Category: Arithmetic core
Language: Verilog
Development status: Alpha
Additional info: none
WishBone compliant: No
WishBone version: n/a
License: LGPL


12/09/2016 - Some rudimentary testing has been done on the fp units at 128 bit and 80 bit precision. It correctly calculates the following:
10.0 + 10.0 = 20.
10.0 * 10.0 = 100.
300.0 / 25.0 = 12.
1.0 + 1.0 = 2
1.0 + 0.0 = 1
1.0 - 1.0/65536 = 0.99998474121095

7/10/2016 - This project is now a bit of a misnomer because it includes cores for IEEE compatible operations as well as the original FT816 core. Rather than start another project I just decided to lump the cores together in this one. FT816Float.v is the original unit which shouldn't require any other modules to use.
added missing redor64 function for floating point unit

3/24/2016 - Added FloatToInt and IntToFloat cores with single cycle latency

FT816 floating point accelerator consists of two ninety-six bit floating point accumulators between which floating point or fixed point operations occur. Basic operations include ADD, SUB, MUL, DIV, FIX2FLT, FLT2FIX, SWAP, NEG and ABS. The floating point accumulators operate as a memory mapped device placed by default between $FEA200 and $FEA2FF. The floating point accelerator communicates through a byte wide data port and twenty-four bit address port. It was intended for use primarily with smaller byte oriented cpu’s like the 65xx, 68xx series in order to provide them with some floating point capability.

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