DDR2 mem controller for Digilent Genesys Board
Project maintainers
Details
Name: genesys_ddr2
Created: May 3, 2013
Updated: May 6, 2013
SVN Updated: May 8, 2013
SVN: Browse
Latest version: download (might take a bit to start...)
Statistics: View
Bugs: 0 reported / 0 solved
Created: May 3, 2013
Updated: May 6, 2013
SVN Updated: May 8, 2013
SVN: Browse
Latest version: download (might take a bit to start...)
Statistics: View
Bugs: 0 reported / 0 solved
Star3you like it: star it!
Other project properties
Category:Memory core
Language:Verilog
Development status:Beta
Additional info:FPGA proven
WishBone compliant: Yes
WishBone version: n/a
License: LGPL
Language:Verilog
Development status:Beta
Additional info:FPGA proven
WishBone compliant: Yes
WishBone version: n/a
License: LGPL
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