i8255 realisation in Verilog

Nov 25, 2009	There is new fix coming soon, which will provide properly reading data from device while ports configured as output.	Bersenev, Dmitry
Nov 22, 2009	Updated svn with assignments fixes. Code contains a lot of junk entities and useless stuff - it's all for the future or just my old thoughts.	Bersenev, Dmitry
Nov 21, 2009	Updated description.	Bersenev, Dmitry
Nov 21, 2009	I'll upload entire Xilinx project soon.	Bersenev, Dmitry
Nov 21, 2009	Uploaded svn. There are only two files now: device and testbench. Supports only 0 mode for Group A and Group B. All signals same as in real device(inverted too). Warning: 'data' must be provided before nWR will be placed on the pin in write mode.	Bersenev, Dmitry
Nov 21, 2009	Updated Description with link to datasheets site.	Bersenev, Dmitry
Nov 17, 2009	And excuse me for word 'realisation' with s instead of z))))	Bersenev, Dmitry
Nov 17, 2009	All operations are triggered by the nRD or nWR, when nCS comes to the pin.	Bersenev, Dmitry
Nov 17, 2009	I'm very busy last time)). Pair lines of code nested on my PC. I 'll upload ones around week. Status: realisation of Group A port A completed.	Bersenev, Dmitry

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