LXP32, a lightweight 32-bit CPU core :: Overview

Project maintainers


Name: lxp32
Created: Feb 20, 2016
Updated: Sep 16, 2016
SVN Updated: Feb 21, 2016
SVN: Browse
Latest version: download
Statistics: View

Other project properties

Category: Processor
Language: VHDL
Development status: Beta
Additional info: Design done, FPGA proven, Specification done
WishBone compliant: Yes
WishBone version: n/a
License: Others


A lightweight, open source 32-bit CPU IP core optimized for FPGA implementation.


  • described in portable VHDL-93, not tied to any particular vendor;
  • 3-stage pipeline;
  • 256 registers implemented as a RAM block;
  • simple instruction set with less than 30 distinct opcodes;
  • separate instruction and data buses, optional instruction cache;
  • WISHBONE compatible;
  • 8 interrupts with hardwired priorities;
  • optional divider.


  • synthesizable RTL description;
  • documentation;
  • automated verification environment (self-checking testbench);
  • software tools (assembler/linker, disassembler) with source code.


LXP32 is distributed under the terms of the MIT license.

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