nec ir remote control decoder
Project maintainers
Details
Name: nec_ir_decoder
Created: Oct 4, 2015
Updated: Oct 6, 2015
SVN Updated: Oct 6, 2015
SVN: Browse
Latest version: download (might take a bit to start...)
Statistics: View
Bugs: 0 reported / 0 solved
Created: Oct 4, 2015
Updated: Oct 6, 2015
SVN Updated: Oct 6, 2015
SVN: Browse
Latest version: download (might take a bit to start...)
Statistics: View
Bugs: 0 reported / 0 solved
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Other project properties
Category:Communication controller
Language:Verilog
Development status:Beta
Additional info:Design done, FPGA proven
WishBone compliant: No
WishBone version: n/a
License: LGPL
Language:Verilog
Development status:Beta
Additional info:Design done, FPGA proven
WishBone compliant: No
WishBone version: n/a
License: LGPL
Description
The NEC IR transmission protocol decoding circuit.
The protocol
* a 9ms leading pulse burst (16 times the pulse burst length used for a logical data bit)
* a 4.5ms space
* the 8-bit address for the receiving device
* the 8-bit logical inverse of the address
* the 8-bit command
* the 8-bit logical inverse of the command
* a final 562.5µs pulse burst to signify the end of message transmission.
System clock 50Mhz
Tested on a Altera DE0 Nano Board.
Repeat codes are yet to be implemented.
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