NPI graphics controller :: Overview

Project maintainers


Name: npigrctrl
Created: Apr 28, 2008
Updated: Jul 20, 2009
SVN Updated: Mar 10, 2009
SVN: Browse
Latest version: download
Statistics: View

Other project properties

Category: Video controller
Language: VHDL
Development status: Stable
Additional info: FPGA proven
WishBone compliant: No
WishBone version: n/a


The design provides basic video function.


- Configurable resolution up to 1600x1400
- Configurable pixel width 16,32 bit per pixel
- Configurable Burst Size and NPI width
- Stride support
- Direct memory access through Xilinx NPI channel
- Support Spartan3x family, Virtex4, Virtex5
- Demo design and bitstream available for EUS FS, ML403, ML405 and ML505


- Resolutions: 640x480x32/16; 800x600x32/16; 1024x768x32/16; 1600x1200x16
- Tested platforms Spartan3E, Virtex4, Virtex5
- Design is available in VHDL - XPS core

To do

- Docs
- Add virtual DMA engine
- Add multilayer support with an alpha-blending
- Accelerator pipe
- Graphical Library Support (Allegro and AGG)

AGG Demo

The ML405 board AGG demo example that demonstrates clipping to multiple rectangular regions. The example is rendered at PPC. The resolution is 1280x1024x32bits without HW accelerator.

The demos can be downloaded at:

ml405.rar AGG Demo
eus_FS - Spartan 3E AGG Demo resolution 800x600x32
eus_FS - Spartan 3E AGG Demo resolution 800x600x16 - agg_demo_eus_fs_16bits.rar
Spartan3AN - AGG Demo resolution 800x600x12bit resolution

After download unpack the file, initiate FPGA by downloading bitstream and download demo software by XMD:

- cd demo_app_1
- dow executable.elf
- run

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