Numbert sort device O(N) :: Overview

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Name: numbert_sort_device
Created: Apr 13, 2014
Updated: May 10, 2014
SVN Updated: Aug 22, 2014
SVN: Browse
Latest version: download
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Other project properties

Category: Arithmetic core
Language: Verilog
Development status: Beta
Additional info: Design done, FPGA proven
WishBone compliant: No
WishBone version: n/a
License: LGPL


// number sorting device, sequential, 2*N clocks for N
// linear buffer implementation
// sequential, stable, can be partly readed, decreasing order
// reset is not implemented
// see sort_stack_algorithm.png to catch the idea

// number sorting, tree-like implementation, sequential,
// energy efficient (theoreticaly)
// see sort_tree_algorithm.png to catch the idea


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