openGFX430 :: Overview

Project maintainers


Name: opengfx430
Created: Aug 3, 2016
Updated: Nov 25, 2016
SVN Updated: Nov 3, 2016
SVN: Browse
Latest version: download
Statistics: View

Other project properties

Category: Video controller
Language: Verilog
Development status: Alpha
Additional info: FPGA proven
WishBone compliant: No
WishBone version: n/a
License: BSD



The openGFX430 is a synthesizable Graphic controller written in Verilog and tailored for the openMSP430 core.

GFX Design Structure
An example implementation based on the DE0-Nano-SoC and LT24 daughter board from Terasic can be found in the openMSP430 FPGA section (see here).

Features & TODOs


  • Support of the following graphic modes:
    • 16bpp
    • 8bpp
    • 4bpp
    • 2bpp
    • 1bpp
  • Smart address generation unit for fast indirect memory access.
  • GPU allowing hardware FILL, COPY and COPY_TRANSPARENT operations.
  • Supports the LT24 Terasic daughter card.


In no particular priority order:
  • RTL:
    • Add support popular video interfaces (i.e. probably SPI and VGA in addition to LT24).
    • Character processing unit.
    • Hardware cursor
  • Others:
    • Add proper block level verification environment.
    • Documentation.



The complete tar archive of the project can be downloaded here (OpenCores account required).

The following SVN command can be run from a console (or GUI):

svn export opengfx430


  • The Core's ChangeLog lists the Video Controller updates.
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