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Overview

Details

Name: or1k
Created: Sep 25, 2001
Updated: Mar 1, 2012
SVN Updated: Feb 24, 2011
SVN: Browse
Latest version: download (might take a bit to start...)
Statistics: View
Bugs: 166 reported / 166 solved

★ Star 0 you like it: star it!

Other project properties

Category: Processor
Language: Verilog
Development status: Stable
Additional info: ASIC proven, Design done, FPGA proven, Specification done
WishBone compliant: Yes
WishBone version: n/a
License: LGPL

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