PLBv46 to Wishbone Bridge :: Overview

Project maintainers


Name: plbv46_to_wb_bridge
Created: Jul 25, 2008
Updated: Mar 5, 2010
SVN Updated: Mar 10, 2009
SVN: Browse
Latest version: download
Statistics: View

Other project properties

Category: System on Chip
Language: VHDL
Development status: Beta
Additional info: FPGA proven
WishBone compliant: Yes
WishBone version: n/a

PLBv46 to Wishbone Bridge

This is a simple CoreConnect PLBv46 to Wishbone bridge that can allow Wishbone peripherals to be used on Xilinx processor designs. It conforms to the sub-set of the PLBv46 specification adopted by Xilinx in the EDK.


- PLBv46 Slave Attachment (non bursting)
- 32-bit interface to PLBv46 bus.
- 32-bit interface to Wishbone bus.

- Supports
- Handling of Retries.
- User can set the retry wait time.
- User can set number of times to retry
- Result of unsuccessful retry is a PLBv46 bus error ack.
- Handling of Bus Errors
- User can set how long to wait for a bus-time out (no WB ack)
- Results in a PLBv46 Bus Error


- New

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