Random Pulse Generator :: Overview

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Name: random_pulse_generator
Created: Mar 26, 2015
Updated: Apr 22, 2015
SVN Updated: Mar 27, 2015
SVN: Browse
Latest version: download
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Other project properties

Category: Other
Language: Verilog
Development status: Stable
Additional info: Design done, FPGA proven
WishBone compliant: No
WishBone version: n/a
License: LGPL


Poisson process generator. The time between each pair of consecutive pulses has an exponential distribution with desired rate. Тhе auxiliary pseudo-random uniform generator is based on 32-bit LFSR. The deign is tested on MICROSEMI IGLOO2 FPGA. Histogram of the number of clocks between output pulses: Title Result of simulation for the rate of one pulse per 16 clocks (parameter LN2_PERIOD=16): Simulated waveform

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