*Reed Solomon Decoder (204,188) :: Overview

Project maintainers


Name: reed_solomon_decoder
Created: Jul 5, 2009
Updated: Nov 23, 2009
SVN Updated: Apr 11, 2010
SVN: Browse
Latest version: download
Statistics: View

Other project properties

Category: ECC core
Language: Verilog
Development status: Stable
Additional info: Design done, FPGA proven
WishBone compliant: No
WishBone version: n/a
License: GPL


• Reed Solomon Decoder (204,188), with T=8.
• Input codeword length is 204 bytes and output length is 188 bytes.
• Corrects up to 8 byte errors per input codeword.
• Code generator polynomial: (x + λ) (x + λ^2) (x + λ^3) ... (x + λ^16).
• Field generator polynomial: x^8+ x^4+ x^3+ x^2+1.
• This version of the Reed Solomon core is distributed under the GPL license.
An optimized and considerably more advanced version, which may be
customized on request for different code generator polynomials, is
available under a commercial license.

Synthesis Results

• Design estimated Gate count is 52,400 gates and total memory bits are 12,432 bits.

• Synthesis Results on Xilinx Spartan 3A DSP:

o Number of occupied slices: 3,397/23,872 (14%).
o Best achievable clock is 12.084 ns.
o Total block RAMs RAMB16BWERs: 11/126 (8%).

• Synthesis Results on Altera Stratix III L150F1152C2:

o Logic utilization 5 %.
o Combinational ALUTs 3,372 / 113,600 (3 %).
o Memory ALUTs 256 / 56,800 ( o Dedicated logic registers: 2,935 / 113,600 (3 %).
o Total block memory bits 12,432 / 5,630,976 ( o Best achievable clock is 3.977 ns.


o Verilog RTL files.
o Simulation test bench.
o MATLAB script to generate test vectors.

About the authors

Varkon Semiconductors
Tel: 1-732-447-8611
Web Site:

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