RapidIO IP library
News
| Jun 3, 2015 | Adding note about the repository move to GitHub to the overview page. | Rosenius, Magnus |
| Mar 1, 2015 | I have started a new repository on https://github.com/magro732/OpenRIO/ where we will continue to develop this project. | Rosenius, Magnus |
| Mar 1, 2015 | Aziz has decided to stop working as a maintainer and has passed the responsibility to Piotr Miedzik instead. Thanks for your contribution Aziz! | Rosenius, Magnus |
| Jan 13, 2015 | Adding release notes to the 1.0.2-release. | Rosenius, Magnus |
| Sep 3, 2014 | Adding page with information about current releases and their content. | Rosenius, Magnus |
| Mar 21, 2014 | Changing expected ready period for the EthSwitch due to changed project priorities. | Rosenius, Magnus |
| Oct 14, 2013 | Editing the upcoming IP-cores that will be submitted in a near future. | Rosenius, Magnus |
| Sep 16, 2013 | Added a PCS using an UART transmission channel. | Rosenius, Magnus |
| Sep 16, 2013 | Added a software C-stack that implements the LP-serial protocol. | Rosenius, Magnus |
| Aug 28, 2013 | A pipelined LP-serial code is available as an alpha release. It passes testcases but has not been run on real hardware yet. It is available under branch/parallelSymbols.. | Rosenius, Magnus |
| Jul 13, 2013 | An effort to optimize the LP-serial core (RioSerial) has been initiated. | Rosenius, Magnus |
| Jun 19, 2013 | Adding the recently written PCS code, which connects the RioSerial to the Virtex-6 GTX-Quad (4-Lane SerDes)) | Demirezen, Aziz |
| Feb 8, 2013 | Adding RapidIO core implementing a bridge between a RapidIO network and a Wishbone bus. | Rosenius, Magnus |
| Feb 1, 2013 | Adding basic documentation. | Rosenius, Magnus |
| Jan 10, 2013 | Updating project description with the currently available IP cores and with information about cores that will be released in a near future.. | Rosenius, Magnus |
| Jan 10, 2013 | Adding RapidIO core implementing the channel independent parts of the LP-serial physical layer specification. | Rosenius, Magnus |
| Jan 9, 2013 | Adding RapidIO packet buffering IP core component, RioPacketBuffer and its testbench. It implements a packet FIFO used to store in- and outbound packets. | Rosenius, Magnus |
| Jan 9, 2013 | Adding the first IP core component, RioSwitch and its testbench. It implements packet switching between ports. | Rosenius, Magnus |
| Jan 8, 2013 | Updating project description. | Rosenius, Magnus |
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