OpenCores

Generic AXI to AHB bridge :: Overview

Project maintainers

Details

Name: robust_axi2ahb
Created: Apr 13, 2011
Updated: Dec 29, 2017
SVN Updated: Jul 3, 2011
SVN: Browse
Latest version: download (might take a bit to start...)
Statistics: View
Bugs: 1 reported / 0 solved

★ Star 0 you like it: star it!

Other project properties

Category: System on Chip
Language: Verilog
Development status: Alpha
Additional info: none
WishBone compliant: No
WishBone version: n/a
License: LGPL

Description

Generic AXI to AHB bridge. Built according to input parameters: AXI command depth, data bits, etc. Supports error on illegal AHB bursts and AHB slave error. The source files are written in RobustVerilog, a free RobustVerilog parser can be downloaded from http://www.provartec.com/edatools

© copyright 1999-2018 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.