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RS232 :: Overview

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Details

Name: rs232_interface
Created: Aug 29, 2010
Updated: Apr 29, 2015
SVN Updated: Jul 3, 2012
SVN: Browse
Latest version: download (might take a bit to start...)
Statistics: View
Bugs: 8 reported / 2 solved

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Other project properties

Category: Communication controller
Language: VHDL
Development status: Stable
Additional info: FPGA proven
WishBone compliant: No
WishBone version: n/a
License: LGPL

Description

This is a small UART to byte uPC interface (compliant with RS232 and RS3232 CI's).
Ideal to use with soft/hard processors in a FPGA project.

Designed to sync internal clock of RX path. Independent clock sources (TX/RX).

uPC Interface

TX:
- TX data;
- TX request;
- TX end of send;

RX:
- RX data;
- RX data ready (data valid);

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