rtfSimpleUart :: Overview

Project maintainers


Name: rtfsimpleuart
Created: Sep 12, 2011
Updated: Nov 16, 2013
SVN Updated: Dec 18, 2015
SVN: Browse
Latest version: download
Statistics: View

Other project properties

Category: Communication controller
Language: Verilog
Development status: Beta
Additional info: Design done, FPGA proven
WishBone compliant: Yes
WishBone version: n/a
License: BSD


This is a simple uart core which includes a baud generator. The core uses a fixed format: 1 start,8 data, 1 stop bit.
+ baudX8/X16 mode selects in runtime

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