RXAUI Interface and XAUI to RXAUI Interface Adapter :: Overview

Project maintainers


Name: rxaui_interface_and_xaui_to_rxaui_interface_adapter
Created: Mar 31, 2009
Updated: Oct 22, 2009
SVN Updated: Apr 2, 2009
SVN: Browse
Latest version: download
Statistics: View

Other project properties

Category: Communication controller
Language: Verilog
Development status: Mature
Additional info: ASIC proven, Design done, FPGA proven, Specification done
WishBone compliant: No
WishBone version: n/a


RXAUI interface uses two 6.25Gbps SERDES lanes to carry 10GE, instead of using four 3.125Gbps SERDES lanes.
This enables a high port count lower power multi 10GE SOCs.

This projects provides the specifications of RXAUI interface and the verilog code for an adapter from
a XAUI to RXAUI interface

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