*Small 1-wire (onewire) master, with Altera tools integration :: Overview

Project maintainers


Name: sockit_owm
Created: Jul 13, 2010
Updated: Feb 16, 2011
SVN Updated: Jun 26, 2011
SVN: Browse
Latest version: download
Statistics: View

Other project properties

Category: Communication controller
Language: Verilog
Development status: Stable
Additional info: Design done, FPGA proven, Specification done
WishBone compliant: Yes
WishBone version: n/a
License: LGPL


This IP implements the 1-wire communication protocol (
A more detailed documentation is provided in "doc/sockit_owm.odt".

RTL features:
- small RTL, should fit into a CPLD
- Avalon MM bus, Wishbone compatible with a simple adapter
- timed reset, presence, write/read bit transfers
- overdrive
- power supply (strong pull-up)

SOPC Builder integration

Nios II EDS integration:
- port of the 1-wire open domain kit version 3.10b
- interrup driven or polling driver
- uCOS-II support (only partialy tested)

The source code and documentation are available on github:

© copyright 1999-2017, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.