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SPDIF Transmitter :: Overview

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Details

Name: spdif_transmitter
Created: Jul 12, 2015
Updated: Jul 13, 2015
SVN Updated: Mar 28, 2016
SVN: Browse
Latest version: download (might take a bit to start...)
Statistics: View
Bugs: reported / solved

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Other project properties

Category: Communication controller
Language: Verilog
Development status: Planning
Additional info: none
WishBone compliant: No
WishBone version: n/a
License: GPL

Description

This is a simple SPDIF transmitter module written in Verilog which supports 16-bit audio samples.

This module can either generate its own audio clock by dividing down clk_i or can use an external audio clock to drive the output stream via audio_clk_i.

For external clocking mode, the audio_clk_i clock rate should be:

32KHz - 4.096MHz
44.1KHz - 5.6448MHz
48KHz - 6.144MHz
Note that in external clocking mode, the frequency of clk_i must be more than 4 x audio_clk_i frequency.

For internal clocking mode, the clk_i input is divided to roughly the right frequency required for chosen the sample rate. This isn't going to be exact!

Testing

No testbench is provided. This IP was tested on a Pioneer VSX D510 over TOSLINK and also with other non-branded D/A converters.

Configuration

CLK_RATE_KHZ - Clock speed (clk_i) in KHz
AUDIO_RATE - Audio sample rate, e.g. 44100 or 48000
AUDIO_CLK_SRC - Can be INTERNAL or EXTERNAL

Size / Performance

With the default configuration...

- the design contains 69 flops, 3 adders, 2 comparators, 11 multiplexers (according to ISE).

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