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SPI Master/Slave Interface :: Bugtracker

Request(s)
Date Title Status Assigned to Submitted by
Dec 20, 2017 How to reset after missed bits? OPENED nathanieltagg
Jan 3, 2017 OPENED dudyB
May 8, 2013 OPENED manasa41
Jul 31, 2011 Verify SLAVE continuous transfer mode CLOSED jdoin jdoin
Bug(s)
Date Title Status Assigned to Submitted by
Jan 4, 2017 false transaction OPENED jdoin dudyB
Jan 3, 2017 false transaction OPENED dudyB
Jan 3, 2017 no clock on transfer sequence OPENED dudyB
Jan 3, 2017 no clock ontransfer sequence OPENED dudyB
May 19, 2016 Testbench Out of Date OPENED jdoin elias.koegel
Apr 27, 2014 Problem with reset SPI MASTER OPENED jdoin jcc18
Aug 29, 2011 MISO top-bit preload CLOSED jdoin jdoin
Aug 8, 2011 SLAVE Continuous Tranfer CLOSED jdoin jdoin
Aug 4, 2011 assert PREFETCH >= 2 CLOSED jdoin ameziti
Jul 18, 2011 CPHA='1' CLOSED jdoin jdoin
Jun 13, 2011 CPHA effect CLOSED jdoin jleemaster
Idea(s)
Date Title Status Assigned to Submitted by
Sep 24, 2011 state encoding OPENED jdoin jdoin
Reminder(s)
Date Title Status Assigned to Submitted by
Aug 2, 2011 Documentation OPENED jdoin jdoin
Jul 11, 2011 Verify MISO top speed CLOSED jdoin jdoin
Jul 8, 2011 Single clock CLOSED jdoin jdoin
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