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SSP_UART :: Overview

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Details

Name: ssp_uart
Created: Nov 1, 2013
Updated: Apr 26, 2014
SVN Updated: Apr 26, 2014
SVN: Browse
Latest version: download
Statistics: View

Other project properties

Category: Communication controller
Language: Verilog
Development status: Mature
Additional info: Design done, FPGA proven
WishBone compliant: No
WishBone version: n/a
License: LGPL

Description

This project provides a full-function UART. The UART provides direct support for a two-wire or a four-wire RS-232 style full-duplex serial interface, but it also provides direct support for a half-duplex RS-485 serial interface. In the RS-232 mode, automatic flow control can be enabled, and the UART will assert RTS when data is available to transmit and wait for CTS to be returned before the transmitter is enabled. In the RS-485 mode, the drive enable of the RS-485 driver is asserted and deasserted automatically.

In both operating modes, the UART supports the use of receive timeouts, RTO. In the RS-485 mode, the RTO function will also inhibit the transmitter until the timeout is asserted. This feature allows easy use of the UART with industrial automation protocols such as Modbus RTU and Profibus that specify minimum inter-packet gaps. The RTO unit of the UART provides a means by which the inter-packet gap can be programmed in multiples of the serial frame size. In other words, the UART RTO unit is programmed in character times to delay, and the programmed frame size is used in the implementation of the delay. For example, if a the serial format is set as 8E1, i.e. Profibus, then the serial frame is 11 bits in length: start, 8 data, 1 parity, and 1 stop. An inter-packet delay of 3 character times is set for the RTO count, so the total delay from the trailing edge of the last received character's stop bit to the leading edge of the start bit of the next transmit character is 33 bit times. This UART automatically sets the frame size to 11 and then uses a counter to generate count down pulses to a second counter which is set for 3. The result is an accurate 33 bit time delay.

The UART also allows independently set FIFO depths for the transmit and receive FIFOs. Interrupts based on various FIFO depth thresholds can also be set so that the interrupt rate can be controlled by the application. Interrupts can be enabled for various conditions: Receive Timeout, Receive FIFO Half Full, Transmit FIFO Half Empty, and Transmit FIFO Empty. The values used for generating FIFO half full interrupts are actually programmable. External user-supplied logic is required to map the interrupt requests onto the interrupt service bus of the application in which the UART is being used; the UART interrupt status registers are available over the communications interface, but are also outputs of the module.

Full documentation of the UART is available in the descriptions provided in SSP_UART module header and those of the functional sub-modules which are used to construct it. A detailed specification and user's guide is included in the Docs section of the SVN repository. Finally, rudimentary testbenches for the SSP_UART and critical sub-modules are also included.

Updates

Updated comments and removed dead code.

Synthesis/PAR Results

The SSP_UART is used in a number of commercial projects. (A demonstration of its use in a system-on-chip project is contained in the M16C5x project elsewhere on opencores.org.) As indicated above, it is a full function UART with capabilities similar to those of a 16C550 UART, but extended with independently configurable FIFO depths for transmit and receive, an interface specifically designed so that it can function as Synchronous Serial Peripheral to an NXP LPC 21xx ARM microcontroller, and additional test and monitoring capabilities. The synthesis/PAR results for the UART provided in this section provide only typical results with regards to size and speed. These characteristics of the SSP_UART are very much dependent on the synthesis and PAR settings of the application/system-on-chip in which the module is being instantiated. For the particular values shown below, the FIFO depths are set to 64 bytes for both the transmit and receive signal paths. Furthermore, the FIFOs are implemented using the DPSFmcCE module, also found here on opencores.org, which uses distributed RAM in a dual-port configuration. If there are sufficient block RAM resources, and LUTs are in short supply, the DPSFmnCE FIFOs can be replaced with block RAM FIFOs. The BRSFmnCE project here on opencores.org is an example of a compatible FIFO implementation that uses block RAMs rather than distrubuted LUT RAM for the FIFO memory.



Module Level Utilization
Module Level UtilizationSat Nov 2 11:56:38 2013



ModulePartitionSlicesSlice RegLUTsLUTRAMBRAMMULT18X18BUFGDCM
[-] SSP_UART/
217/47781/255195/5430/1360/00/02/20/0
  BRG
16/1617/1724/240/00/00/00/00/0
  [-] INT
6/244/235/110/00/00/00/00/0
       FE1
4/44/41/10/00/00/00/00/0
       FE2
2/23/31/10/00/00/00/00/0
       RE1
3/33/31/10/00/00/00/00/0
       RE2
3/33/31/10/00/00/00/00/0
       RE3
3/33/31/10/00/00/00/00/0
       RE4
3/33/31/10/00/00/00/00/0
  RCV
43/4334/3459/590/00/00/00/00/0
  RED1
4/44/42/20/00/00/00/00/0
  RED2
4/44/42/20/00/00/00/00/0
  RED3
5/54/42/20/00/00/00/00/0
  RED4
4/44/42/20/00/00/00/00/0
  RED5
4/44/42/20/00/00/00/00/0
  RF1
55/5520/2093/9372/720/00/00/00/0
  TF1
49/4920/2085/8564/640/00/00/00/0
  TMR
21/2117/1727/270/00/00/00/00/0
  XMT
31/3123/2339/390/00/00/00/00/0



Timing Constraints


Met Constraint CheckWorst Case Slack Best Case Achievable Timing Errors Timing Score
Yes Autotimespec constraint for clock net Clk_BUFGP SETUP/HOLD N/A / 0.726ns 5.547ns N/A / 0 0/0
Yes Autotimespec constraint for clock net SSP_SCK_BUFGP SETUP/HOLD N/A / 1.244ns 5.415ns N/A / 0 0/0



Xilinx Design Summary
M16C5x Project Status (11/02/2013 - 10:20:16)
Project File: M16C5x.ise Current State: Placed and Routed
Module Name: SSP_UART
  • Errors:
 
Target Device: xc3s50a-4vq100
  • Warnings:
 
Product Version: ISE 10.1.03 - Foundation
  • Routing Results:
All Signals Completely Routed
Design Goal: Balanced
  • Timing Constraints:
All Constraints Met
Design Strategy: Xilinx Default (unlocked)
  • Final Timing Score:
 
M16C5x Partition Summary [-]
No partition information was found.
 
Device Utilization Summary [-]
Logic UtilizationUsedAvailableUtilizationNote(s)
Number of Slice Flip Flops 255 1,408 18%  
Number of 4 input LUTs 542 1,408 38%  
Logic Distribution     
Number of occupied Slices 352 704 50%  
    Number of Slices containing only related logic 352 352 100%  
    Number of Slices containing unrelated logic 0 352 0%  
Total Number of 4 input LUTs 543 1,408 38%  
    Number used as logic 406      
    Number used as a route-thru 1      
    Number used for Dual Port RAMs 136      
Number of bonded IOBs
Number of bonded 44 68 64%  
Number of BUFGMUXs 2 24 8%  
 
Performance Summary [-]
Final Timing Score: 0 Pinout Data: Pinout Report
Routing Results: All Signals Completely Routed Clock Data: Clock Report
Timing Constraints: All Constraints Met    
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentSat Nov 2 10:18:44 2013059 Warnings (5 new, 56 filtered)7 Infos (2 new, 0 filtered)
Translation ReportCurrentSat Nov 2 10:18:51 2013000
Map ReportCurrentSat Nov 2 10:19:08 2013069 Warnings (0 new, 0 filtered)5 Infos (0 new, 0 filtered)
Place and Route ReportCurrentSat Nov 2 10:19:29 2013   
Static Timing Report     
Bitgen Report     

Date Generated: 11/02/2013 - 10:20:16

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