Campbell, Ken

SystemVerilog Directed Test Bench

## Description

The SystemVerilog Directed Test Bench.  
This project contains an exact duplication of the VHDL Test Bench Package parser and usage model. This enables users to create a simple test environment for verification efforts using SV. This also enables scripts that were used on the VHDL system to be reused in a SV environment. (providing the same functionality is coded in the SV environment.)  
  
Current state is Beta, please report any problems to the bug tracking system so I can address issues.


<h2 id="description">Description</h2>
<p>The SystemVerilog Directed Test Bench.<br />
This project contains an exact duplication of the VHDL Test Bench Package parser and usage model.  This enables users to create a simple test environment for verification efforts using SV.  This also enables scripts that were used on the VHDL system to be reused in a SV environment.  (providing the same functionality is coded in the SV environment.)<br />
<br />
Current state is Beta,  please report any problems to the bug tracking system so I can address issues.</p>


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SystemVerilog Directed Test Bench

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