SystemC/Verilog Random Number Generator :: Overview

Project maintainers


Name: systemc_rng
Created: Aug 19, 2004
Updated: Apr 9, 2010
SVN Updated: Mar 10, 2009
SVN: Browse
Latest version: download (might take a bit to start...)
Statistics: View
Bugs: 1 reported / 0 solved

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Other project properties

Category: Other
Language: Verilog
Development status: Stable
Additional info: FPGA proven
WishBone compliant: No
WishBone version: n/a
License: LGPL


A SystemC/Verilog random number generator based on the combination of a LFSR and a CASR with very good statisticall properties.
Based on the Thomas E. Tkacik work available at:

This work is given by Universidad Rey Juan Carlos (Spain)


- Very good statisticall properties
- Synthesizable


- Done

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