gen_vectorial :: Overview

Project maintainers


Name: vectorial_generator
Created: Mar 22, 2013
Updated: Mar 31, 2013
SVN Updated: Mar 30, 2014
SVN: Browse
Latest version: download
Statistics: View

Other project properties

Category: Other
Language: VHDL
Development status: Stable
Additional info: Design done, FPGA proven
WishBone compliant: No
WishBone version: n/a
License: Others


Vectorial generator:

-Interface: bit or bus
-Configuration: dynamic
-Applications: waveform generator, serial or parallel communication


-Included in the own .vhd headfile


-It is necessary to adjust the following type which defines the input size (it affects to area resources):

SUBTYPE valores_vector IS INTEGER RANGE -1 TO nat_synth_65536'high; -- values range for each sample (always from -1)
TYPE vector_integer IS ARRAY (nat_synth_128'high DOWNTO 0) OF valores_vector; -- number of samples*2


SUBTYPE nat_synth_65536 IS NATURAL RANGE 0 TO 65535;
SUBTYPE nat_synth_2048 IS NATURAL RANGE 0 TO 2047;
SUBTYPE nat_synth_16 IS NATURAL RANGE 0 TO 15;

© copyright 1999-2017, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.