Versatile FIFO :: Overview


Name: versatile_fifo
Created: Mar 31, 2009
Updated: Feb 11, 2014
SVN Updated: Nov 4, 2010
SVN: Browse
Latest version: download (might take a bit to start...)
Statistics: View
Bugs: 2 reported / 2 solved

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Other project properties

Category: Memory core
Language: Verilog
Development status: Stable
Additional info: FPGA proven, Specification done
WishBone compliant: No
WishBone version: n/a
License: LGPL



The FIFO implementation outlined in this document can easily be configured to suit the following

  • asynchronous FIFO with different clock domains for read and write sides
  • synchronous FIFO with programmable flags
  • multiple FIFO sharing the same memory resource

This FIFO can easily be extended to have common wishbone interface for all individual FIFO channels.

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