OpenCores

8051 Slave to Wishbone Master Interface

Project maintainers

Details

Name: wb_mcs51
Created: Mar 3, 2008
Updated: Jul 25, 2008
SVN Updated: Mar 10, 2009
SVN: Browse
Latest version: download (might take a bit to start...)
Statistics: View
Bugs: 0 reported / 0 solved
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Other project properties

Category:Other
Language:Verilog
Development status:Stable
Additional info:Design done, FPGA proven
WishBone compliant: Yes
WishBone version: n/a
License:

Description

Interface an 8051-compatible microcontroller with the Wishbone bus.

Features

- Multiplexed 8051 address/data bus to Wishbone Master
- Very simple, very small.
- Since 8051 has no way to add additional wait-states via an external pin, the Wishbone must be fast enough to complete the cycle in time for the 8051.

Status

- Tested with Silicon Labs C8051 Microcontroller and Xilinx Coolrunner2 CPLD.
- Tested with Silicon Labs C8051 Microcontroller and Xilinx Spartan3 FPGA.
- this core is used in the Altair32 Front Panel: www.altair32.com