OpenCores

External parallel port to internal wishbone master interface

Project maintainers

Details

Name: wbc_parallel_master
Created: Jun 22, 2008
Updated: Jun 26, 2008
SVN Updated: Mar 10, 2009
SVN: Browse
Latest version: download (might take a bit to start...)
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Bugs: 0 reported / 0 solved
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Other project properties

Category:System controller
Language:VHDL
Development status:Alpha
Additional info:Specification done
WishBone compliant: No
WishBone version: n/a
License: GPL

Description

This core is intended to be used as an interface between some functionality in an FPGA and an external microcontroller.

The external microcontroller provides a simple 8bit interface to control some functions within the FPGA. These functions are communicating using a wishbone compatible bus within the FPGA.

Features

- 8 bit external interface to a simple parallel port of a regular microcontroller
- two cycle external bus transfers: first address, then data
- interrupt request flag
- bidirectional external data port
- wishbone compatible master interface to connect internal cores

Status

2008-06-23: Specification document available