Mulcock, Andrew

wishbone out port from b3 spec

## Description

Are you using Wishbone, do you need some simple 'slaves' to test your bus with ?  
  
Well, the Wishbone spec, appendix B3, has VHDL examples of Wishbone outports, and memories.  
  
This is the code from B3 ! saves one copying the PDF each time.

## Features

\- Can be simulated and can be synthesised.  

## Status

Simulated in XST 9.2 sp 4  
Synthesised to Spartan FPGA.


<h2 id="description">Description</h2>
<p>Are you using Wishbone, do you need some simple 'slaves' to test your bus with ?<br />
<br />
Well, the Wishbone spec, appendix B3, has VHDL examples of Wishbone outports, and memories. <br />
<br />
This is the code from B3 ! saves one copying the PDF each time. </p>
<h2 id="features">Features</h2>
<p>- Can be simulated and can be synthesised.<br />
</p>
<h2 id="status">Status</h2>
<p>Simulated in XST 9.2 sp 4<br />
Synthesised to Spartan FPGA.<br />
<br />
</p>


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wishbone out port from b3 spec

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