OpenCores

Parameterizable adder tree

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Details

Name: adder_tree
Created: Mar 17, 2018
Updated: Mar 23, 2018
SVN Updated: Mar 27, 2018
SVN: Browse
Latest version: download (might take a bit to start...)
Statistics: View
Bugs: 0 reported / 0 solved
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Other project properties

Category:Arithmetic core
Language:Verilog
Development status:Stable
Additional info:
WishBone compliant: No
WishBone version: n/a
License: LGPL

Description

Parameterizable Verilog module that calculate sum of N variables. It works in streaming mode and can used in convolution (FIR) and in phased array systems.