BCD adder :: Overview

Project maintainers


Name: bcd_adder
Created: Sep 2, 2016
Updated: May 19, 2017
SVN Updated: Sep 20, 2016
SVN: Browse
Latest version: download (might take a bit to start...)
Statistics: View
Bugs: reported / solved

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Other project properties

Category: Arithmetic core
Language: VHDL
Development status: Planning
Additional info: none
WishBone compliant: No
WishBone version: n/a
License: LGPL


The goal of this project is to design a generic BCD adder that can adds two BCD inputs and a carry in to produce a BCD sum and a carry out.

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