ALMatary, Hesham

Edge Processor (MIPS)

## Description

![Title](/usercontent/img/1393794016)  
Edge is a microarchitecture implementation for mips1 ISA.  
It has a 32 bit datapath divided into five pipeline stages operating at 50 MHz frequency.  
Supporting timer and other interrupt types and exceptions is implemented through co-processor0.  
Edge has been tested and verified on Atlys that has a Spartan-6 XC6SLX45 FPGA.  
For the Atlys board, UART driver is provided to communicate with PC at 115200 baud rate.  
![Schematic ](/usercontent/img/1404060923)  
  
Youtube link for simple C programs running \[1\]  
https://www.youtube.com/watch?v=Hxwq2KWzycU


<h2 id="description">Description</h2>
<img src="/usercontent/img/1393794016" alt="Title" />
 

Edge is a microarchitecture implementation for mips1 ISA. 
It has a 32 bit datapath divided into five pipeline stages operating at 50 MHz frequency. 
Supporting timer and other interrupt types and exceptions is implemented through co-processor0. 
Edge has been tested and verified on Atlys that has a Spartan-6 XC6SLX45 FPGA. 
For the Atlys board, UART driver is provided to communicate with PC at 115200 baud rate. 

<img src="/usercontent/img/1404060923" alt="Schematic " />
 

 

Youtube link for simple C programs running [1] 

https://www.youtube.com/watch?v=Hxwq2KWzycU

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Edge Processor (MIPS)

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