Anti-Logarithm (square-root), base-2, single-cycle :: Overview

Project maintainers


Name: fast_antilog
Created: Aug 8, 2010
Updated: Jan 28, 2011
SVN Updated: Aug 8, 2010
SVN: Browse
Latest version: download (might take a bit to start...)
Statistics: View
Bugs: reported / solved

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Other project properties

Category: Arithmetic core
Language: Verilog
Development status: Stable
Additional info: Design done
WishBone compliant: No
WishBone version: n/a
License: LGPL


A fast (single-cycle) base-2 antilog function.

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Doesn't run quite as fast as my Log code: 166MHz, vs. 250MHz for the log. Registering the input would bring that up. Takes about the same resources as the log.

To do a single-cycle square-root, first take the log. Then, divide that result by 2 (shift), and take the antilog. Tada...

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