ClaiRISC - runs 12bit opcode PIC family. :: Overview

Project maintainers


Name: lwrisc
Created: Feb 8, 2008
Updated: Feb 13, 2009
SVN Updated: Mar 10, 2009
SVN: Browse
Latest version: download (might take a bit to start...)
Statistics: View
Bugs: 1 reported / 0 solved

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Other project properties

Category: Processor
Language: Verilog
Development status: Stable
Additional info: Design done, FPGA proven
WishBone compliant: No
WishBone version: n/a


This ClaiRISC is a soft MCU core which runs PIC 12bits instruction.Compared with PIC16F57 ,This core has the same number of register file while ports and timer are not avilable,but you can map your device register to the REGINSTER_FILE address.It uses about 240LES in ALTERA CYCLONE device.


- The architecture of ClaiRISC is very clair.
- Written with verilog-2001.
- Two stages pipeline.
- Not support interrupt now.
- Each instruction run in one clock except some "test and skip" instructions which run in two clock.
- Synthesized and tested in ALTERA cyclone device at 50MHZ using 240 LES (4%)and works well.

IMAGE: 200735153855.JPG

FILE: 200735153855.JPG
DESCRIPTION: In the name of Leifeng


DESCRIPTION: Architecture of ClaiRISC

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