Puffitsch, Wolfgang

McAdam's RISC Computer Architecture

## Description

McAdam's RISC Computer Architecture (marca) is a simple 16-bit microprocessor, implementing a load/store instruction set architecture and featuring a 4-stage pipeline.

## Features

\- 16 16-bit registers  
\- Harvard architecture  
\- all memories on-chip  
\- 16KB instruction ROM  
\- 8KB data RAM  
\- 256 byte data ROM  
\- load/store instruction set architecture  
\- 75 instructions  
\- 16 interrupt vectors  
\- 4-stage pipeline

## Status

\- running on an Altera Cyclone FPGA


<h2 id="description">Description</h2>
<p>McAdam's RISC Computer Architecture (marca) is a simple 16-bit microprocessor, implementing a load/store instruction set architecture and featuring a 4-stage pipeline.</p>
<h2 id="features">Features</h2>
<p>- 16 16-bit registers<br />
- Harvard architecture<br />
 - all memories on-chip<br />
 - 16KB instruction ROM<br />
 - 8KB data RAM<br />
 - 256 byte data ROM<br />
- load/store instruction set architecture<br />
 - 75 instructions<br />
- 16 interrupt vectors<br />
- 4-stage pipeline</p>
<h2 id="status">Status</h2>
<p>- running on an Altera Cyclone FPGA</p>


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McAdam's RISC Computer Architecture

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