8-bit microcontroller with extended peripheral set

Description

The goal of this project is to create a very well documented, fully synthesizable VHDL model of an 8-bit microcontroller with extended peripheral set. The model should be highly configurable, making it possible to exclude unused peripheral units. These features make it a very good choice for SoC (System-on-a-chip) designs and for purely educational purposes.
An assembler and a testbench describing the behavior of both program and data memory are provided.

http://www-user.tu-chemnitz.de/~dimo/opencorescpu8.gif

Features

- assembler
- testbench describing the behavior of program and data memory
- Makefile for synthesis with XST (Xilinx) and simulation with Modelsim (Mentor Graphics)

Status

- Implemented Modules
src/control.vhd
src/alu.vhd
src/pc.vhd
src/reg.vhd
src/ram_control.vhd
src/components.vhd
src/cpu_types.vhd
src/ram.vhd
src/rom.vhd
src/processor_E.vhd
src/processor_tb.vhd

- Implemented Instructions
NOP -- no operation
NEG -- bitwise nagation
AND -- bitwise logical AND
EXOR -- bitwise Exclusive-OR
OR -- bitwise OR
SRA -- shift left through carry
ROR -- rotate left through carry
ADD -- add without carry
ADDC -- add with carry
JMP addr -- unconditional jump
JMPC addr -- jump if carry set
JMPZ addr -- jump if zero set
LDA const -- load Accumulator Immediate
LDB const -- load Extension Register Immediate
LDA addr -- load Accumulator Direct
LDB addr -- load Extension Register Direct
STA addr -- store Accumulator

- Implemented Peripheral
- Memmory mapped LCD Controller
- PWM Unit
- WDT

History

10.08.2008
- testbench coverage improved
- fixed bug in the ALU

03.07.2008
- new assembler programs added
- improved testbench
- fixed bug in the control unit

02.07.2008
- fixed bug in the register block
- scipts for backannotated simulation added

27.06.2008
- SRAM controller modificated
- overall performance improved (293 clocks for the reference multiplication program)