M2G - Media Oriented Systems Transport (MOST) IP core :: Overview

Project maintainers


Name: most_core
Created: Jul 2, 2004
Updated: Mar 28, 2010
SVN Updated: Jul 4, 2018
SVN: Browse
Latest version: download (might take a bit to start...)
Statistics: View
Bugs: 1 reported / 0 solved

★ Star 0 you like it: star it!

Other project properties

Category: Communication controller
Language: VHDL
Development status: Planning
Additional info: none
WishBone compliant: Yes
WishBone version: n/a


With the M2G protocol a high performance, very scalable and easy to implement multi media transport system for in car use shall be defined. Inspired by the MOST protocol (Media Oriented Systems Transport) ( but with many innovative improvements it shall be proved that with already existing technologies a far higher bandwidth for in car communication is possible.

Any OEM (car manufacturer) and Tier1 are welcome to participate in this project and to support my work. If you find mistakes in my documentation inform me, please.


MOST currently specifies three different speed grades: 25, 50 and 150 Mbps (INIC25..INIC150 chips). By adoption of existing high speed data transmission technologies like PCIe, SATAII, USB3 and RapidIO it is expected to boost this bandwidth beyond 2 Gbps independent whether fiber optics or copper transmission lines are used.

Additionally the following demands must be kept in mind:
* open protocol spec
* scalable from 150 Mbps up to above 3 Gbps
* support for 44.1, 48 or 96kHz frame rate
* tunnelling of other bus systems like Ethernet or DTCP
* independent from transmission media (optical or copper; DC free)
* reuse of existing M messaging software
* CDR (clock data recovery), source synchronous or oversampling possible
* for FPGA and ASIC
* dynamic bandwidth usage
* save and deterministic arbitration mechanisms
* protecting the ECU controller from high bandwidths streams and high event rates
* EMI reduction (e.g. data scrambling and error detection/recovery)

The steps

The following steps will be required:

1. Requirements analysis, analysis of available technologies [in progress; 85%]
2. Protocol specification [todo]
3. Proof of some physical principles [todo]
4. Simulation of node behavior [todo]
5. Protocol review [todo]
6. IP core specification [todo]
7. Simulation and real life test specification [todo]
8. Programming and simulation [todo]
9. Synthesis for FPGA [todo]
10. Real life test and validation [todo]
11. Bug fixing [todo]
12. Documentation [todo]
13. Promotion [todo]

© copyright 1999-2018, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.