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*OpenRISC 1000 :: Overview

Details

Name: or1k
Created: Sep 25, 2001
Updated: Apr 4, 2018
SVN Updated: Apr 28, 2018
SVN: Browse
Latest version: download (might take a bit to start...)
Statistics: View
Bugs: 166 reported / 166 solved

★ Star 4 you like it: star it!

Other project properties

Category: Processor
Language: Verilog
Development status: Stable
Additional info: ASIC proven, Design done, FPGA proven, Specification done
WishBone compliant: Yes
WishBone version: n/a
License: LGPL

Status of the OpenRISC 1000

WARNING!
The development of the OpenRISC moved to OpenRISC.io
The files contained in this repository are most likely outdated.
For more information try to get in contact with one of the former developers (project maintainer).

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