PWM :: Overview

Project maintainers


Name: pwm
Created: Sep 19, 2012
Updated: Oct 13, 2012
SVN Updated: Oct 5, 2012
SVN: Browse
Latest version: download (might take a bit to start...)
Statistics: View
Bugs: reported / solved

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Other project properties

Category: Other
Language: Verilog
Development status: Alpha
Additional info: Design done, FPGA proven, Specification done
WishBone compliant: Yes
WishBone version: n/a
License: LGPL


Pulse Width Modulator
• Work as one PWM or one timer.
• 16 bits main counter.
• PWM/Timer can choose between Wishbone interface clock or external clock as working clock.
• PWM can choose between dedicated duty cycle input or internal register as source of duty cycle.
• Duty cycle and period can be changed at runtime.
• Hosted through Wishbone slave interface.
• Working clock's frequency can be divided to at most 1/65535 of original frequency.
• Period register also serves as timer target register when module is in timer mode.

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