RISC Microcontroller

Project maintainers

yapzihe

Details

Name: riscmcu
Created: Apr 13, 2002
Updated: Sep 17, 2004
SVN Updated: Mar 10, 2009
SVN: Browse
Latest version: download (might take a bit to start...)
Statistics: View
Bugs: 0 reported / 0 solved

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Other project properties

Category:Processor
Language:
Development status:Stable
Additional info:
WishBone compliant: No
WishBone version: n/a
License:

Description

RISCMCU is based on the features and instruction set of Atmel AVR AT90S1200 RISC Microcontroller.

AT90S1200 vs RISCMCU
Specification	AT90S1200	RISCMCU
Instructions	89	92
General P. Registers	32	16
Program ROM	512 words	512 words
SRAM	None	128 bytes
Hardware Stack	3 Level Deep	4 Level Deep
I/O Ports	2 (15 pins)	3 (24 pins)
Addressing Modes	5	7
Speed	4 / 12 MHz	12 MHz ¹
8-bit Timer	1	1
External Interrupt	1	1
Implementation	CMOS	FPGA ²
Others	Analog Comparator, Watchdog Reset, EEPROM, Internal Pull-Up Resistor	None

Note 1 : Based on the report of Synopsys FPGA Express
Note 2 : Altera EPF10K20RC240-4 Device (on Altera UP1 Education Board)

Block Diagram

Downloads

Description	Download
Complete VHDL Source Code	RISCMCU_vhdl.tar.gz
Documentation - Thesis (PDF, 668KB)	RISCMCU_Thesis.pdf
Slides Presentation (PDF, 112KB)	RISCMCU_Presentation.pdf
Simple Calculator ASM File	simple_calculator.asm
Simple Memory Game ASM File	memory_game.asm
HEX2MIF C Source Code	hex2mif.c

* To download any of the files, please right click on the link and select 'Save Target As'.

Please visit CVSWEB - RISCMCU to download more files.

Datasheets

AVR RISC Microcontroller Instruction Set

Atmel AVR AT90S1200 (Complete)

Atmel AVR AT90S2313 (Complete)

FLEX 10K Embedded Programmable Logic Family

University Program Design Laboratory Package

Links

Atmel AVR RISC Microcontrollers

AVR Assembler and AVR Studio Download Page

MAX+plus II BASELINE Download Page

Important!!!

You will NOT be able to synthesis (compile) the project with MaxPlus II. The project was synthesized with Synopsis FPGA Express 3.4. At that time, Altera was providing free license for it. However, Altera no longer provides free license file. If you are lucky, your university might have purchased it and make it available in the lab. Else, you will need to purchase it yourself.

But the good news is, Altera Quartus II is able to synthesis the project and it is FREE! Get it here. You will need to do some minor modifications to modules v_rom and v_ram. Comment out or remove the 'inclock' and 'outclock' lines in port(). Else, Quartus will complaint.

Click here to visit the Frequently Ask Questions (FAQ) Section.