S80186 :: Overview

Project maintainers


Name: s80186
Created: Nov 30, 2017
Updated: Dec 14, 2017
SVN Updated: Nov 30, 2017
SVN: Browse
Latest version: download (might take a bit to start...)
Statistics: View
Bugs: 1 reported / 1 solved

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Other project properties

Category: Processor
Language: Verilog
Development status: Beta
Additional info: Design done, FPGA proven, Specification done
WishBone compliant: No
WishBone version: n/a
License: GPL


The S80186 IP core is a compact, 80186 binary compatible core, implementing the full 80186 ISA suitable for integration into FPGA/ASIC designs. The core executes most instructions in far fewer cycles than the original Intel 8086, and in many cases, fewer cycles than the 80286. The core is supplied as synthesizable SystemVerilog, along with a C++ reference model, extensive tests, a reference BIOS implementation and reference FPGA designs. The core is released under the GPLv3 license.

- Binary compatible with the Intel 80186 core
* FreeDOS
* OpenWatcom/GCC ia16-elf compilers
- Separate data/IO and instruction busses
- 1MB addressable segmented memory
- 64KB addressable IO space
- Lock signal for atomic accesses
- 256 external interrupts
- 1 non-maskable interrupt
- Debug interface suitable
- JTAG TAP compatible
- Register/Memory access
- Execution control
- FPGA builds (Intel Cyclone V)
* 60MHz FMax
*~1800 ALMs

- Full synthesizable SystemVerilog
- C++ reference model
- FPGA reference designs for Terasic DE0-Nano and DE0-CV
- Extensive test suite verified against C++ model, RTL and FPGA
- Complete Docker build environments
- Full development documentation and programmers guide

Reference Design
- SDR SDRAM controller
- SD card for fixed disk emulation
- 8259 PIC-lite controller
- 8254 PIT-lite timer operating in mode 2 only.
- CGA controller with VGA output
- PS/2 controller


The S80186 is a 16-bit architecture with 8 16-bit general purpose registers, 4 segment registers allowing access to 1MB of physical memory. The architecture uses a variable length instruction encoding allowing for high code density. The core is a microcoded design using a small amount of logic and a flexible microassembler. The microsequencer is used to implement an efficient debug interface that can be connected to a JTAG TAP or disabled if required.

Full compatibility with 80186 ISA is provided, implementing all instructions, traps, faults and interrupts and known errata. Undocumented instructions such as SETALC are also implemented.

Source is maintained at subversion will be synced from github.

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