Simple Capture/Compare Timer :: Overview

Project maintainers


Name: scct
Created: Jun 10, 2015
Updated: Dec 3, 2015
SVN Updated: Jun 15, 2015
SVN: Browse
Latest version: download (might take a bit to start...)
Statistics: View
Bugs: reported / solved

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Other project properties

Category: Other
Language: Verilog
Development status: Stable
Additional info: Design done, FPGA proven, Specification done
WishBone compliant: No
WishBone version: n/a
License: GPL


SCCT is a Simple Capture/Compare Timer written in Verilog. It provides multiple capture/compare channels that use a common counter. Events occurring in the single channels thus can be related to a global time base. SCCT is developed as an IP core that can be attached to the Altera Avalon bus.

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