UoS Educational Processor :: Overview

Project maintainers


Name: uos_processor
Created: Dec 5, 2017
Updated: Dec 9, 2017
SVN Updated: Dec 5, 2017
SVN: Browse
Latest version: download (might take a bit to start...)
Statistics: View
Bugs: reported / solved

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Other project properties

Category: Processor
Language: VHDL
Development status: Mature
Additional info: Design done, FPGA proven, Specification done
WishBone compliant: No
WishBone version: n/a
License: LGPL


* 8-bit, 4 register processor
* Von Neumann architecture
* 3 clock cycle per instruction
* 16-bit instruction set (inspired by x86 ISA)
* Direct, indirect, immediate, register addressing
* Customizable instructions
* External memory bus (for program/data)
* I/O interface (as in microcontrollers)
* Implemented in VHDL
* Synthesizable

Top level system:
* Designed for Nexys 4
* Instantiates a processor, RAM and RAM editor
* Allows to edit the RAM using the Nexys 4 switches, push buttons and 7-segment display
* Allows to visualize the CPU registers (RA-RD), memory bus address and instruction register on the 7-segment display, as well as ALU flags and sequencing state on the LEDs
* Interfaces the CPU output port to the Nexys 4 LEDs
* Interfaces the CPU input port to the Nexys 4 switches

All the content, including VHDL, lecture material (powerpoint), images and others is licensed under LGPL 2.1.

* This design has been used since 2014 in the module "Digital Systems and Microprocessor Design" at the University of Sussex (UK) with about ~50 students per year using it.

Original author: Daniel Roggen.

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